Integrated circuits are currently the electronic products that are innovated at the fastest speed in the world, whilst a memory device is always the typical product that represents the development level of integrated circuit technology. Advancement of design and manufacturing process of integrated circuits makes it possible to continuously improve storage capacity and performance of SRAM. SRAM becomes the maximum amount of volatile memory device used as computer cache for its fast reading and writing speed. Additionally, SRAM also has been widely applied in electronic products of aviation, telecommunication and consumer electronic goods.
Along with rapid development in the areas of aerospace industry and semiconductor technology, various electronic devices have been applied in space of very harsh conditions, in which various radioactive particles disperse. Radioactive effect would lead to confusion of data inversion in memory cells of semiconductor memory devices and also lead to data transmission error of an entire logic circuit. Accordingly, SRAM designers now are faced with such an unavoidable issue as how to improve radiation resistance of SRAM.
Most of the conventional SRAMs make use of six-transistor units, whose structure is shown in FIG. 1, and are composed of two clamp inverters (M1 and M5 constituting an inverter, whilst M2 and M6 constituting a second inverter) and another two transmission transistors (M3 and M4). A world line WL controls M3 and M4; M3 and M4 are turned on upon operations of reading and writing. At the time of reading, two bit lines BLB and BL are both pre-charged to a high electric level. When 1 is written in, BL=1, BLB=0; when 0 is written in, BL=0, BLB=1.
For the current SRAM memory cells, BL and BLB are pre-charged to Vdd/2 at the time of reading operations. The voltage of the node storing 0 rises because of voltage-split principles in transistors, which consequently reduces the static noise margin. As shown in FIG. 1, two bit lines BL and BLB are individually charged to Vdd/2 at the time of reading operations. If the memory value of a memory node Q on the left is 1, the memory value of the memory node QB on the right is 0, then WL=1, M5 is turned on at the time of reading; since Q stores 1, the gate voltage of the M2 transistor is in an ON state all the time; when BLB reads 0 stored in QB, it is charged to a high electric level; therefore, M2 and M4 form a discharge path, and the voltage of QB rises from 0. If the voltage of QB rises to a certain level, it may turn M1 on, and the potential of the node Q is driven down, which consequently causes data stored in the entire SRAM flip and thence leads to data transmission errors.
Therefore, at the time of reading, the voltage of a node storing 0 rises to a certain level between 0 and Vdd/2, the exact figure of which depends on the conducting resistance between M2 and M4. In this case, if this node is further interfered by a noise voltage, flip is more likely to happen; consequently, the static noise margin is reduced. Likewise, the issue of voltage change also happens to storage nodes at the time of reading “1”. As shown in FIG. 1, BL and BLB are pre-charged to Vdd/2 before the stored data is read; if Q=1, QB=0, then M3 and M5 are turned on, and the potential of Q point is at a level between Vdd/2 and Vdd, the exact figure of which depends on the conducting resistances of M3 and M5.
FIG. 2 illustrates an SRAM cell designed on the basis of a dual interlocked storage cell (DICE) structure in the prior art, in which four inverters constitute four storage nodes A, B, C, D. According to the design scheme, the potentials of A and C should be the same, while the potentials of B and D should be the same. Discussion about different situations is to be given below on the basis of different initial values of A, B, C, D.
□ Assume initial conditions are that A=1, B=0, C=1, D=0. It can be seen that A controls the turning on of N8 and drives D node down to 0; and at the meantime, D controls the turning on of P1 and drives Node A up to a high electric level; therefore, A and D control each other when they are respectively 1 and 0. Likewise, B and C also control each other. {circle around (2)} If A=0, B=1, C=0, D=1, then A=0 enables P2 to drive B up to 1, while B turns N1 on and drives A down to 0; Likewise, C and D also control each other in this case.
In situation □, if B flips to 1, it cannot be restored except by a feedback from C to B. If B flips to 0, it may turn P3 on because of a fairly large instant current, and C is driven up to 1. In this case, the entire BC feedback becomes ineffective. Because A and D are a pair of controlling nodes, while B and C are a pair of controlling nodes. A and D are incapable of restoring flip of B. The similar problem would also happen in situation {circle around (2)}.
Accordingly, it is desirable to propose an SRAM cell structure that has a relatively large static noise margin and is resistant of influence from initial electric level of nodes.